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» Full-Chip Multilevel Routing for Power and Signal Integrity
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ICASSP
2009
IEEE
14 years 1 months ago
Cross-layer optimization of wireless fading ad-hoc networks
This paper introduces an algorithm to approximately find optimal wireless networks in presence of fading. Joint optimization of application level rates, routes, link capacities, ...
Nikolaos Gatsis, Alejandro Ribeiro, Georgios B. Gi...
SLIP
2004
ACM
14 years 16 days ago
Optical solutions for system-level interconnect
Throughput, power consumption, signal integrity, pin count and routing complexity are all increasingly important interconnect issues that the system designer must deal with. Recen...
Ian O'Connor
DAC
1999
ACM
14 years 8 months ago
A Novel VLSI Layout Fabric for Deep Sub-Micron Applications
We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout "fabric" scheme eliminate...
Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton,...
DAC
2004
ACM
14 years 8 months ago
Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs
The negative effect of electromigration on signal and power line lifetime and functional reliability is an increasingly important problem for the physical design of integrated cir...
Goeran Jerke, Jürgen Scheible, Jens Lienig
DATE
2002
IEEE
144views Hardware» more  DATE 2002»
14 years 2 days ago
Design Automation for Deepsubmicron: Present and Future
Advancing technology drives design technology and thus design automation EDA. How to model interconnect, how to handle degradation of signal integrity and increasing power densi...
Ralph H. J. M. Otten, Raul Camposano, Patrick Groe...