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VTS
2003
IEEE
122views Hardware» more  VTS 2003»
14 years 2 months ago
A Reconfigurable Shared Scan-in Architecture
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
Samitha Samaranayake, Emil Gizdarski, Nodari Sitch...
DATE
2009
IEEE
94views Hardware» more  DATE 2009»
14 years 3 months ago
Improving compressed test pattern generation for multiple scan chain failure diagnosis
To reduce test data volumes, encoded tests and compacted test responses are widely used in industry. Use of test response compaction negatively impacts fault diagnosis since the e...
Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. ...
VTS
1997
IEEE
133views Hardware» more  VTS 1997»
14 years 1 months ago
ATPG for scan chain latches and flip-flops
A new approach for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking ex...
Samy Makar, Edward J. McCluskey
ASPDAC
2006
ACM
90views Hardware» more  ASPDAC 2006»
14 years 3 months ago
A routability constrained scan chain ordering technique for test power reduction
Abstract— For scan-based testing, the high test power consumption may cause test power management problems, and the extra scan chain connections may cause routability degradation...
X.-L. Huang, J.-L. Huang
ET
2002
77views more  ET 2002»
13 years 8 months ago
Reusing Scan Chains for Test Pattern Decompression
The paper presents a method for testing a system-on-achip by using a compressed representation of the patterns on an external tester. The patterns for a certain core under test ar...
Rainer Dorsch, Hans-Joachim Wunderlich