192 search results - page 9 / 39 » Functional Scan Chain Testing |
DAC
2003
ACM
14 years 10 months ago
2003
ACM
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
ATS
2004
IEEE
14 years 25 days ago
2004
IEEE
Conventional serial connection of internal scan chains brings the power and time penalty. A novel parallel core wrapper design (pCWD) approach is presented in this paper for reduc...
DATE
2002
IEEE
14 years 2 months ago
2002
IEEE
We present a new test resource partitioning (TRP) technique for reduced pin-count testing of system-on-a-chip (SOC). The proposed technique is based on test data compression and o...
DFT
2002
IEEE
14 years 2 months ago
2002
IEEE
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...
ATS
2004
IEEE
14 years 25 days ago
2004
IEEE
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...