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RECONFIG
2009
IEEE
182views VLSI» more  RECONFIG 2009»
14 years 5 months ago
Scalability Studies of the BLASTn Scan and Ungapped Extension Functions
BLASTn is a ubiquitous tool used for large scale DNA analysis. Detailed profiling tests reveal that the most computationally intensive sections of the BLASTn algorithm are the sc...
Siddhartha Datta, Ron Sass
GLVLSI
2005
IEEE
133views VLSI» more  GLVLSI 2005»
14 years 4 months ago
Generating decision regions in analog measurement spaces
We develop a neural network that learns to separate the nominal from the faulty instances of a circuit in a measurement space. We demonstrate that the required separation boundari...
Haralampos-G. D. Stratigopoulos, Yiorgos Makris
ICCAD
1994
IEEE
110views Hardware» more  ICCAD 1994»
14 years 2 months ago
Test pattern generation based on arithmetic operations
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signi cant area overhead and performance degradation...
Sanjay Gupta, Janusz Rajski, Jerzy Tyszer
DAC
2006
ACM
14 years 11 months ago
Timing-based delay test for screening small delay defects
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
ATS
2005
IEEE
191views Hardware» more  ATS 2005»
14 years 4 months ago
Low Transition LFSR for BIST-Based Applications
Abstract—This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within...
Mohammad Tehranipoor, Mehrdad Nourani, Nisar Ahmed