174 search results - page 5 / 35 » Functional Test Generation for Full Scan Circuits |
ICCD
2004
IEEE
14 years 7 months ago
2004
IEEE
This paper shows that by creating functional scan chains at the register-transfer level (RTL), not only the timing of the circuit can be improved, but also the test data compressi...
VTS
1996
IEEE
14 years 2 months ago
1996
IEEE
Designing a testable circuit is often a two step process. First, the circuit is designed to conform to the functional specifications. Then, the testability aspects are added. By t...
ICCD
2006
IEEE
14 years 7 months ago
2006
IEEE
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
ISQED
2006
IEEE
14 years 4 months ago
2006
IEEE
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
DATE
2004
IEEE
14 years 2 months ago
2004
IEEE
This paper presents 3LSSD, a novel, easilyautomatable approach for scan insertion and ATPG of asynchronous circuits. 3LSSD inserts scan latches only into global circuit feedback p...