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» Functional Verification of Large ASICs
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DAC
2002
ACM
14 years 7 months ago
Hole analysis for functional coverage data
One of the main goals of coverage tools is to provide the user with informative presentation of coverage information. Specifically, information on large, cohesive sets of uncovere...
Oded Lachish, Eitan Marcus, Shmuel Ur, Avi Ziv
DAC
2005
ACM
13 years 8 months ago
VLIW: a case study of parallelism verification
Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper...
Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Li...
DAC
2006
ACM
14 years 7 months ago
Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability
- Classical two-variable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuit-bas...
Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, ...
DAC
2004
ACM
14 years 7 months ago
Defining coverage views to improve functional coverage analysis
Coverage analysis is used to monitor the quality of the verification process. Reports provided by coverage tools help users identify areas in the design that have not been adequat...
Sigal Asaf, Eitan Marcus, Avi Ziv
CAV
2004
Springer
108views Hardware» more  CAV 2004»
13 years 10 months ago
Functional Dependency for Verification Reduction
Abstract. The existence of functional dependency among the state variables of a state transition system was identified as a common cause of inefficient BDD representation in formal...
Jie-Hong Roland Jiang, Robert K. Brayton