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ICCAD
1998
IEEE
122views Hardware» more  ICCAD 1998»
13 years 12 months ago
Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits
In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DATPG). Our improvements are achieved by de...
Vamsi Boppana, W. Kent Fuchs
ITC
1998
IEEE
120views Hardware» more  ITC 1998»
13 years 12 months ago
Test generation in VLSI circuits for crosstalk noise
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital c...
Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer
ICCAD
2006
IEEE
126views Hardware» more  ICCAD 2006»
14 years 4 months ago
Exploring linear structures of critical path delay faults to reduce test efforts
It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target pat...
Shun-Yen Lu, Pei-Ying Hsieh, Jing-Jia Liou
ITC
1995
IEEE
104views Hardware» more  ITC 1995»
13 years 11 months ago
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
Nur A. Touba, Edward J. McCluskey
DATE
2005
IEEE
127views Hardware» more  DATE 2005»
14 years 1 months ago
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application
— With increasing process fluctuations in nano-scale technology, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. Desig...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...