138 search results - page 13 / 28 » Functional test generation for delay faults in combinational... |
DSD
2006
IEEE
14 years 1 months ago
2006
IEEE
Testing of high density SoCs operating at high clock speeds is an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when th...
DFT
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper, we propose a new concept of testing only functionally testable transition faults in Broadside Transition testing via a novel constrained ATPG. For each functionally...
VTS
2008
IEEE
14 years 2 months ago
2008
IEEE
— Higher chip densities and the push for higher performance have continued to drive design needs. Transition delay fault testing has become the preferred method for ensuring thes...
DFT
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
ITC
2003
IEEE
14 years 29 days ago
2003
IEEE
: The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture smalldistributed delay de...