138 search results - page 14 / 28 » Functional test generation for delay faults in combinational... |
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
We introduce a novel method of test generation for microprocessors at the RTL using spectral methods. Test vectors are generated for RTL faults, which are the stuck-at faults on i...
ICTAI
2002
IEEE
14 years 19 days ago
2002
IEEE
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
VTS
1996
IEEE
13 years 12 months ago
1996
IEEE
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
DATE
1998
IEEE
13 years 12 months ago
1998
IEEE
A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate le...
ATS
2000
IEEE
14 years 3 days ago
2000
IEEE
Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor design. However, domino logic ...