142 search results - page 26 / 29 » Functional test generation for non-scan sequential circuits |
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
There have been serious concerns recently about the security of microchips from hardware trojan horse insertion during manufacturing. This issue has been raised recently due to ou...
DAC
2005
ACM
13 years 10 months ago
2005
ACM
Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper...
CEC
2010
IEEE
13 years 9 months ago
2010
IEEE
Rather than attempting to evolve a complete program from scratch we demonstrate genetic interface programming (GIP) by automatically generating a parallel CUDA kernel with identica...
FPGA
2005
ACM
14 years 2 months ago
2005
ACM
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
FPL
2001
Springer
14 years 1 months ago
2001
Springer
Abstract. Visual data
ow environments are ideally suited for modeling digital signal processing (DSP) systems, as many DSP algorithms are most naturally speci ed by signal
ow gra...