171 search results - page 4 / 35 » Future Performance Challenges in Nanometer Design |
IPPS
2008
IEEE
2008
IEEE
Modeling and predicting application performance on parallel computers using HPC challenge benchmarks
14 years 1 months ago
A method is presented for modeling application performance on parallel computers in terms of the performance of microkernels from the HPC Challenge benchmarks. Specifically, the a...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best pow...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Customizable processors are being used increasingly often in SoC designs. During the past few years, they have proven to be a good way to solve the conflicting flexibility and p...
IPPS
2002
IEEE
14 years 9 days ago
2002
IEEE
Future high-end computers will offer great performance improvements over today’s machines, enabling applications of far greater complexity. However, designers must solve the cha...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
— As silicon CMOS devices are scaled down into the nanoscale regime, new challenges at both the device and system level are arising. While some of these challenges will be overco...