11 search results - page 1 / 3 » Gate Level Fault Diagnosis in Scan-Based BIST |
DATE
2002
IEEE
13 years 11 months ago
2002
IEEE
A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test v...
ITC
1997
IEEE
13 years 11 months ago
1997
IEEE
A deterministic-partitioning technique and an improved analysis scheme for fault diagnosis in Scan-Based BIST is proposed. The incorporation of the superposition principle to the ...
ITC
2000
IEEE
13 years 11 months ago
2000
IEEE
A deterministic partitioning technique for fault diagnosis in Scan-Based BIST is proposed. Properties of high quality partitions for improved fault diagnosis times are identified...
DFT
2009
IEEE
14 years 1 months ago
2009
IEEE
This paper presents the first implementation of Built-In Self-Test (BIST) of Field Programmable Gate Arrays (FPGAs) using a soft core embedded processor for reconfiguration of the...
DFT
2004
IEEE
13 years 10 months ago
2004
IEEE
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...