694 search results - page 14 / 139 » Gate Sizing Using a Statistical Delay Model |
DAC
2005
ACM
13 years 9 months ago
2005
ACM
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
DAC
1999
ACM
14 years 15 hour ago
1999
ACM
Buffer insertion has become a critical step in deep submicron design, and several buffer insertion/sizing algorithms have been proposed in the literature. However, most of these m...
DATE
2000
IEEE
14 years 3 days ago
2000
IEEE
DAC
2006
ACM
14 years 8 months ago
2006
ACM
We propose a scalable and efficient parameterized block-based statistical static timing analysis algorithm incorporating both Gaussian and non-Gaussian parameter distributions, ca...