694 search results - page 43 / 139 » Gate Sizing Using a Statistical Delay Model |
VLSID
2002
IEEE
14 years 9 months ago
2002
IEEE
Predictive delay analysis is presented for a representative CMOS inverter with submicron device size using PREDICTMOS MOSFET model. As against SPICE, which adopts a time consuming...
ICCAD
2004
IEEE
14 years 5 months ago
2004
IEEE
9, IO]. However, unlike the case with static timing, it is not so easy We show how recent advances in the handling of correlated interval representations of range uncertainty can b...
TSP
2008
13 years 9 months ago
2008
A new framework for designing robust adaptive filters is introduced. It is based on the optimization of a certain cost function subject to a time-dependent constraint on the norm o...
DATE
2006
IEEE
14 years 3 months ago
2006
IEEE
This paper focuses on statistical interconnect timing analysis in a parameterized block-based statistical static timing analysis tool. In particular, a new framework for performin...
VLSID
2005
IEEE
14 years 9 months ago
2005
IEEE
Buffer insertion method plays a great role in modern VLSI design. Many buffer insertion algorithms have been proposed in recent years. However, most of them used simplified delay ...