694 search results - page 53 / 139 » Gate Sizing Using a Statistical Delay Model |
INFOCOM
2009
IEEE
14 years 3 months ago
2009
IEEE
—This paper considers the design of opportunistic packet schedulers for users sharing a time-varying wireless channel from the performance and the robustness points of view. Firs...
DAC
2006
ACM
14 years 10 months ago
2006
ACM
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we pre...
SIGCOMM
1994
ACM
14 years 1 months ago
1994
ACM
Interframe compression techniques, such as those used in MPEG video, give rise to a coded bit stream where picture sizes di er by a factor of 10 or more. As a result, bu ering is ...
ICCAD
1997
IEEE
14 years 18 days ago
1997
IEEE
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
TCAD
2008
13 years 9 months ago
2008
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical...