694 search results - page 7 / 139 » Gate Sizing Using a Statistical Delay Model |
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
Technology scaling, characterized by decreasing feature size, thinning gate oxide, and non-ideal voltage scaling, will become a major hindrance to microprocessor reliability in fu...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
DAC
2004
ACM
13 years 11 months ago
2004
ACM
There is an increased dominance of intra-die process variations, creating a need for an accurate and fast statistical timing analysis. Most of the recent proposed approaches assum...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM