38 search results - page 5 / 8 » Gate sizing with controlled displacement |
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Digital Down Conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algo...
ATS
2000
IEEE
13 years 11 months ago
2000
IEEE
Testing of embedded cores is very difficult in SOC (system-on-a-chip), since the core user may not know the gate level implementation of the core, and the controllability and obse...
RSP
1999
IEEE
13 years 11 months ago
1999
IEEE
Over the past decade, the steady growth rate of FPGA device capacities has enabled the development of multi-FPGA prototyping environments capable of implementing millions of logic...
DATE
2002
IEEE
14 years 9 days ago
2002
IEEE
Advancing technology drives design technology and thus design automation EDA . How to model interconnect, how to handle degradation of signal integrity and increasing power densi...
ATS
2005
IEEE
13 years 9 months ago
2005
IEEE
Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional ...