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FPGA
1997
ACM
142views FPGA» more  FPGA 1997»
13 years 11 months ago
Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond
Process technology advances tell us that the one-million gate Field-Programmable Gate Array (FPGA) will soon be here, and larger devices shortly after that. We feel that current a...
Jonathan Rose, Dwight D. Hill
ISVLSI
2003
IEEE
86views VLSI» more  ISVLSI 2003»
14 years 22 days ago
Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS
SOI (silicon-on-insulator) technology suffers from a number of floating body effects, most notably parasitic bipolar and history effects. These are influenced by the rapidly incre...
Koushik K. Das, Richard B. Brown
DATE
2002
IEEE
102views Hardware» more  DATE 2002»
14 years 13 days ago
Library Compatible Ceff for Gate-Level Timing
Accurate gate-level static timing analysis in the presence of RC loads has become an important problem for modern deep-submicron designs. Non-capacitive loads are usually analyzed...
Bernard N. Sheehan
DAC
2002
ACM
14 years 8 months ago
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, S...
ISMVL
2008
IEEE
111views Hardware» more  ISMVL 2008»
14 years 1 months ago
Multiple Valued Logic Using 3-State Quantum Dot Gate FETs
Abstract—This paper presents fundamental logic structures designed using novel quantum dot gate FETs with three-state characteristics. This three-state FET manifests itself as a ...
John A. Chandy, Faquir C. Jain