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DAC
2006
ACM
14 years 8 months ago
Statistical logic cell delay analysis using a current-based model
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
Hanif Fatemi, Shahin Nazarian, Massoud Pedram
DATE
2009
IEEE
86views Hardware» more  DATE 2009»
14 years 2 months ago
A link arbitration scheme for quality of service in a latency-optimized network-on-chip
Abstract—Networks-on-chip (NoC) for general-purpose multiprocessors require quality of service mechanisms to allow realtime streaming applications to be executed along with laten...
Jonas Diemer, Rolf Ernst
DATE
2008
IEEE
103views Hardware» more  DATE 2008»
14 years 2 months ago
A Mutation Model for the SystemC TLM 2.0 Communication Interfaces
Mutation analysis is a widely-adopted strategy in software testing with two main purposes: measuring the quality of test suites, and identifying redundant code in programs. Simila...
Nicola Bombieri, Franco Fummi, Graziano Pravadelli
COMPSAC
2006
IEEE
14 years 1 months ago
Performance Analysis of an Asynchronous Web Server
Modern Web servers need to process multiple requests concurrently in order to fulfill the workload demands expected of them. Concurrency can be implemented in a Web server using ...
U. Praphamontripong, Swapna S. Gokhale, Aniruddha ...
MOBIWAC
2006
ACM
14 years 1 months ago
Ad hoc routing based on the stability of routes
Some reactive ad hoc protocols allow the discovery and/or storage of multiple paths to the same destination node. The selection of the path to utilize is commonly based on the cri...
Alicia Triviño-Cabrera, Irene Nieves-P&eacu...