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ISCA
2011
IEEE
522views Hardware» more  ISCA 2011»
13 years 10 days ago
CPPC: correctable parity protected cache
Due to shrinking feature sizes processors are becoming more vulnerable to soft errors. Write-back caches are particularly vulnerable since they hold dirty data that do not exist i...
Mehrtash Manoochehri, Murali Annavaram, Michel Dub...
INFOCOM
1999
IEEE
14 years 28 days ago
The TIME-WAIT State in TCP and Its Effect on Busy Servers
Hosts providing important network services such as HTTP and FTP incur a per-connection memory load from TCP that can adversely affect their connection rate and throughput. The mem...
Theodore Faber, Joseph D. Touch, Wei Yue
SODA
1998
ACM
99views Algorithms» more  SODA 1998»
13 years 10 months ago
On-Line File Caching
Consider the following file caching problem: in response to a sequence of requests for files, where each file has a specified size and retrieval cost, maintain a cache of files of ...
Neal E. Young
CASES
2007
ACM
14 years 19 days ago
A low power front-end for embedded processors using a block-aware instruction set
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since inst...
Ahmad Zmily, Christos Kozyrakis
AINA
2005
IEEE
14 years 2 months ago
Global Connectivity for Mobile IPv6-Based Ad Hoc Networks
The IPv6-enabled network architecture has recently attracted much attention. In this paper, we address the issue of connecting MANETs to global IPv6 networks while supporting IPv6...
Chiung-Ying Wang, Cheng-Ying Li, Ren-Hung Hwang, Y...