456 search results - page 6 / 92 » Generating high performance pruned FFT implementations |
VLSID
2006
IEEE
14 years 7 months ago
2006
IEEE
In this paper we present a high-performance, high throughput, and area efficient architecture for the VLSI implementation of the AES algorithm. The subkeys, required for each round...
ISCAS
2003
IEEE
14 years 23 days ago
2003
IEEE
Polyphase IIR structures are known to be very attractive for very high performance filters that can be designed using very few coefficients. This combined with their reduced sensi...
RSP
2005
IEEE
14 years 1 months ago
2005
IEEE
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...
AHS
2007
IEEE
13 years 7 months ago
2007
IEEE
Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entir...
JMLR
2010
13 years 2 months ago
2010
Subgroup discovery aims at finding subsets of a population whose class distribution is significantly different from the overall distribution. A number of multi-class subgroup disc...