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FPL
2007
Springer
99views Hardware» more  FPL 2007»
13 years 11 months ago
Disjoint Pattern Enumeration for Custom Instructions Identification
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. These custom instructions are selected through an analys...
Pan Yu, Tulika Mitra
ICALT
2010
IEEE
13 years 6 months ago
The Design and Application of an Automatic Course Generation System for Large-Scale Education
—In China, the number of online learners who attend formal education has quadrupled in the last 5 years to 8.2 millions until the end of 2008. How can online teachers build and u...
Xiaohong Tan, Carsten Ullrich, Yan Wang, Ruimin Sh...
ASAP
2007
IEEE
134views Hardware» more  ASAP 2007»
13 years 9 months ago
Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications
Network processors utilizing general-purpose instruction-set architectures (ISA) limit network throughput due to latency incurred from cryptography and hashing applications (AES, ...
David Montgomery, Ali Akoglu
HPCA
2006
IEEE
14 years 8 months ago
Software-hardware cooperative memory disambiguation
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
Ruke Huang, Alok Garg, Michael C. Huang
IPPS
2005
IEEE
14 years 1 months ago
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
Hongkyu Kim, D. Scott Wills, Linda M. Wills