1262 search results - page 29 / 253 » Generating instruction sets and microarchitectures from appl... |
MICRO
2008
IEEE
14 years 2 months ago
2008
IEEE
—L1 instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 instruction caches large enough t...
DYNAMO
2000
13 years 9 months ago
2000
Many binary tools, such as disassemblers, dynamiccode generation systems, and executable code rewriters, need to understand how machine instructions are encoded. Unfortunately, sp...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper presents an efficient methodology for estimating the energy consumption of application programs running on extensible processors. Extensible processors, which are incr...
LCTRTS
2009
Springer
14 years 2 months ago
2009
Springer
Dynamic binary translation (DBT) can provide security, virtualization, resource management and other desirable services to embedded systems. Although DBT has many benefits, its r...
ISSS
1999
IEEE
14 years 5 days ago
1999
IEEE
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...