1262 search results - page 7 / 253 » Generating instruction sets and microarchitectures from appl... |
ICCAD
2008
IEEE
14 years 3 months ago
2008
IEEE
— This paper presents a method for correct-by-construction microarchitectural pipelining that handles cyclic systems with dependencies between iterations. Our method combines pre...
CGO
2004
IEEE
13 years 10 months ago
2004
IEEE
Instruction scheduling hardware can be simplified and easily pipelined if pairs of dependent instructions are fused so they share a single instruction scheduling slot. We study an...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-c...
ICCD
2002
IEEE
14 years 3 months ago
2002
IEEE
A variety of factors is making it increasingly difficult and expensive to design and manufacture traditional Application Specific Integrated Circuits (ASICs). This has started a s...
ICCD
2008
IEEE
14 years 4 months ago
2008
IEEE
— Circuit and processor designs will continue to increase in complexity for the foreseeable future. With these increasing sizes comes the use of wide buses to move large amounts ...