647 search results - page 71 / 130 » Generation of BDDs from hardware algorithm descriptions |
AMAI
2004
Springer
14 years 1 months ago
2004
Springer
The paper integrates automatically generated case-splitting expressions, and an efficient translation to CNF, in order to formally verify an out-of-order superscalar processor havi...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. P...
ICCAD
2010
IEEE
13 years 6 months ago
2010
IEEE
Craig Interpolation is a state-of-the-art technique for logic synthesis and verification, based on Boolean Satisfiability (SAT). Leveraging the efficacy of SAT algorithms, Craig In...
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
Abstract--We present a processor-programmable built-in selftest (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circ...
ICIP
2004
IEEE
14 years 9 months ago
2004
IEEE
In this paper we propose and test an action recognition algorithm in which the images of the scene captured by a significant number of cameras are first used to generate a volumet...