Available techniques for testing core-based systems-on-a-chip (SOCs) do not provide a systematic means for synthesising low-overhead test architectures and compact test solutions....
Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jh...
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...
Policy testing and analysis are important techniques for high assurance of correct specification of access control policies. We propose a set of testing and analysis techniques fo...
We present a new method of built-in-self-test (BIST) for sequential circuits and system-on-a-chip (SOC) using characteristic faults and circuitspecific spectral information in th...
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...