68 search results - page 11 / 14 » Generation of compact test sets with high defect coverage |
120
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ICCAD
1999
IEEE
15 years 8 months ago
1999
IEEE
Available techniques for testing core-based systems-on-a-chip (SOCs) do not provide a systematic means for synthesising low-overhead test architectures and compact test solutions....
134
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VTS
2000
IEEE
15 years 8 months ago
2000
IEEE
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...
124
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ICSE
2007
IEEE-ACM
16 years 4 months ago
2007
IEEE-ACM
Policy testing and analysis are important techniques for high assurance of correct specification of access control policies. We propose a set of testing and analysis techniques fo...
121
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ICCAD
2002
IEEE
16 years 1 months ago
2002
IEEE
We present a new method of built-in-self-test (BIST) for sequential circuits and system-on-a-chip (SOC) using characteristic faults and circuitspecific spectral information in th...
153
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ATS
2003
IEEE
15 years 9 months ago
2003
IEEE
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...