68 search results - page 8 / 14 » Generation of compact test sets with high defect coverage |
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...
ITC
1995
IEEE
13 years 11 months ago
1995
IEEE
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
We investigate a new fault ordering heuristic for test generation in full-scan circuits. The heuristic is referred to as the accidental detection index. It associates a value ADI ...
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
As silicon process technology scales deeper into the nanometer regime, hardware defects are becoming more common. Such defects are bound to hinder the correct operation of future ...
VTS
1999
IEEE
13 years 11 months ago
1999
IEEE
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...