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IFIP
2000
Springer
14 years 11 days ago
A Product Family Approach to Graceful Degradation
Design of gracefully degrading systems, where functionality is gradually reduced in the face of faults, has traditionally been a very difficult and error-prone task. General appro...
William Nace, Phil Koopman
VLSID
2002
IEEE
107views VLSI» more  VLSID 2002»
14 years 9 months ago
Automatic Model Refinement for Fast Architecture Exploration
We present a methodology and algorithms for automatic refinement from a given design specification to an architecture model based on decisions in architecture exploration. An arch...
Junyu Peng, Samar Abdi, Daniel Gajski
ASPDAC
2008
ACM
97views Hardware» more  ASPDAC 2008»
13 years 10 months ago
A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures
Horizontally Partitioned Caches (HPCs) are a promising architectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt
DAC
2004
ACM
14 years 2 months ago
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...
Philip Brisk, Adam Kaplan, Majid Sarrafzadeh
DATE
2009
IEEE
159views Hardware» more  DATE 2009»
14 years 3 months ago
Design and implementation of a database filter for BLAST acceleration
— BLAST is a very popular Computational Biology algorithm. Since it is computationally expensive it is a natural target for acceleration research, and many reconfigurable archite...
Panagiotis Afratis, Constantinos Galanakis, Euripi...