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» Geometric programming for circuit optimization
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CEC
2009
IEEE
14 years 4 months ago
Gate-level optimization of polymorphic circuits using Cartesian Genetic Programming
— Polymorphic digital circuits contain ordinary and polymorphic gates. In the past, Cartesian Genetic Programming (CGP) has been applied to synthesize polymorphic circuits at the...
Zbysek Gajda, Lukás Sekanina
ASPDAC
2008
ACM
122views Hardware» more  ASPDAC 2008»
13 years 11 months ago
Total power optimization combining placement, sizing and multi-Vt through slack distribution management
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...
Tao Luo, David Newmark, David Z. Pan
DATE
2003
IEEE
108views Hardware» more  DATE 2003»
14 years 3 months ago
Generalized Posynomial Performance Modeling
This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. The coefficient set ...
Tom Eeckelaert, Walter Daems, Georges G. E. Gielen...
ISQED
2005
IEEE
125views Hardware» more  ISQED 2005»
14 years 3 months ago
A New Method for Design of Robust Digital Circuits
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin C...
EUROGP
2004
Springer
135views Optimization» more  EUROGP 2004»
14 years 3 months ago
Reusing Code in Genetic Programming
Abstract. In this paper we propose an approach to Genetic Programming based on code reuse and we test it in the design of combinational logic circuits at the gate-level. The circui...
Edgar Galván López, Riccardo Poli, C...