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ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
14 years 5 months ago
A code refinement methodology for performance-improved synthesis from C
Although many recent advances have been made in hardware synthesis techniques from software programming languages such as C, the performance of synthesized hardware commonly suffe...
Greg Stitt, Frank Vahid, Walid A. Najjar
MICRO
2002
IEEE
143views Hardware» more  MICRO 2002»
14 years 1 months ago
Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor
Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functio...
Enric Gibert, F. Jesús Sánchez, Anto...
JUCS
2000
120views more  JUCS 2000»
13 years 8 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
RECOMB
2007
Springer
14 years 9 months ago
Minimizing and Learning Energy Functions for Side-Chain Prediction
Abstract. Side-chain prediction is an important subproblem of the general protein folding problem. Despite much progress in side-chain prediction, performance is far from satisfact...
Chen Yanover, Ora Schueler-Furman, Yair Weiss
PADS
2004
ACM
14 years 2 months ago
Space-Parallel Network Simulations Using Ghosts
We discuss an approach for creating a federated network simulation that eases the burdens on the simulator user that typically arise from more traditional methods for defining sp...
George F. Riley, Talal M. Jaafar, Richard M. Fujim...