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» Global Routing with Crosstalk Constraints
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ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
14 years 3 months ago
A technique for low energy mapping and routing in network-on-chip architectures
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
Krishnan Srinivasan, Karam S. Chatha
ICCAD
2000
IEEE
109views Hardware» more  ICCAD 2000»
14 years 2 months ago
General Models for Optimum Arbitrary-Dimension FPGA Switch Box Designs
–An FPGA switch box is said to be hyper-universal if it is routable for all possible surrounding multi-pin net topologies satisfying the routing resource constraints. It is desir...
Hongbing Fan, Jiping Liu, Yu-Liang Wu
DAC
2009
ACM
14 years 10 months ago
O-Router:an optical routing framework for low power on-chip silicon nano-photonic integration
In this work, we present a new optical routing framework, O-Router for future low-power on-chip optical interconnect integration utilizing silicon compatible nano-photonic devices...
Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, D...
ASPDAC
2005
ACM
89views Hardware» more  ASPDAC 2005»
13 years 11 months ago
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they cons...
Yan Lin, Fei Li, Lei He
ASPDAC
2005
ACM
78views Hardware» more  ASPDAC 2005»
13 years 11 months ago
Timing driven track routing considering coupling capacitance
Abstract— As VLSI technology enters the ultra-deep submicron era, wire coupling capacitance starts to dominate self capacitance and can no longer be neglected in timing driven ro...
Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra