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ISCA
2010
IEEE
236views Hardware» more  ISCA 2010»
14 years 1 months ago
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
Enric Herrero, José González, Ramon ...
MICRO
2000
IEEE
121views Hardware» more  MICRO 2000»
14 years 4 days ago
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
Rajeev Balasubramonian, David H. Albonesi, Alper B...
NAS
2007
IEEE
14 years 2 months ago
An Efficient SAN-Level Caching Method Based on Chunk-Aging
: SAN-level caching can manage caching within a global view so that global hot data can be identified and cached. However, two problems may be encountered in the existing SAN-level...
Jiwu Shu, Yang Wang 0009, Wei Xue, Yifeng Luo
WAIM
2004
Springer
14 years 1 months ago
Performance Evaluations of Replacement Algorithms in Hierarchical Web Caching
Abstract. Web caching plays an important role in many network services. Utilization of the cache in each level (server, proxy, and client) of network forms a web caching hierarchy....
Haohuan Fu, Pui-on Au, Weijia Jia
ICCD
2008
IEEE
118views Hardware» more  ICCD 2008»
14 years 5 months ago
Adaptive techniques for leakage power management in L2 cache peripheral circuits
— Recent studies indicate that a considerable amount of an L2 cache leakage power is dissipated in its peripheral circuits, e.g., decoders, word-lines and I/O drivers. In additio...
Houman Homayoun, Alexander V. Veidenbaum, Jean-Luc...