: This paper presents a synthesis algorithm for pipelined circuits. The circuit is specified as a collection of independent, looselycoupled modules connected by queues. The synthe...
-- Due to the increasing demand for mobility in the area of distributed systems, the use of wireless communication gains in importance. We present a wireless real-time communicatio...
Existing slotted channel access schemes in wireless networks assume that slot boundaries at all nodes are synchronized. In practice, relative clock drifts among nodes cause slot mi...
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Multiple Clock Domain (MCD) processors are a promising future alternative to today’s fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor ...
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas...