403 search results - page 45 / 81 » Gradient clock synchronization |
IFIP
1999
Springer
14 years 27 days ago
1999
Springer
: This paper presents a synthesis algorithm for pipelined circuits. The circuit is specified as a collection of independent, looselycoupled modules connected by queues. The synthe...
WISES
2004
13 years 10 months ago
2004
-- Due to the increasing demand for mobility in the area of distributed systems, the use of wireless communication gains in importance. We present a wireless real-time communicatio...
BROADNETS
2006
IEEE
14 years 2 months ago
2006
IEEE
Existing slotted channel access schemes in wireless networks assume that slot boundaries at all nodes are synchronized. In practice, relative clock drifts among nodes cause slot mi...
ICCAD
2005
IEEE
14 years 5 months ago
2005
IEEE
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
ASPLOS
2004
ACM
14 years 2 months ago
2004
ACM
Multiple Clock Domain (MCD) processors are a promising future alternative to today’s fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor ...