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VLSID
2002
IEEE
78views VLSI» more  VLSID 2002»
16 years 4 months ago
Optimization of Test Accesses with a Combined BIST and External Test Scheme
External pins for test are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architectu...
Makoto Sugihara, Hiroto Yasuura
ISCC
2009
IEEE
163views Communications» more  ISCC 2009»
15 years 11 months ago
Distributed parallel scheduling algorithms for high-speed virtual output queuing switches
Abstract—This paper presents a novel scalable switching architecture for input queued switches with its proper arbitration algorithms. In contrast to traditional switching archit...
Lotfi Mhamdi, Mounir Hamdi
ISSTA
2009
ACM
15 years 11 months ago
Precise pointer reasoning for dynamic test generation
Dynamic test generation consists of executing a program while gathering symbolic constraints on inputs from predicates encountered in branch statements, and of using a constraint ...
Bassem Elkarablieh, Patrice Godefroid, Michael Y. ...
GECCO
2007
Springer
214views Optimization» more  GECCO 2007»
15 years 10 months ago
Portfolio allocation using XCS experts in technical analysis, market conditions and options market
Schulenburg [15] first proposed the idea to model different trader types by supplying different input information sets to a group of homogenous LCS agent. Gershoff [12] investigat...
Sor Ying (Byron) Wong, Sonia Schulenburg
MICRO
2006
IEEE
100views Hardware» more  MICRO 2006»
15 years 10 months ago
Serialization-Aware Mini-Graphs: Performance with Fewer Resources
Instruction aggregation—the grouping of multiple operations into a single processing unit—is a technique that has recently been used to amplify the bandwidth and capacity of c...
Anne Bracy, Amir Roth