477 search results - page 74 / 96 » Guideline: Multiple Hierarchies |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
In recent years, increasing manufacturing density has allowed the development of Multi-Processor Systems-on-Chip (MPSoCs). Application-Specific Instruction Set Processors (ASIPs)...
IJCNN
2006
IEEE
14 years 1 months ago
2006
IEEE
— In-place learning is a biologically inspired concept, meaning that the computational network is responsible for its own learning. With in-place learning, there is no need for a...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
— An effectively designed and efficiently used memory hierarchy, composed of scratch-pads or cache, is seen today as the key to obtaining energy and performance gains in data-do...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
RTAS
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper, we study the problem of allocating end-toend bandwidth to each of multiple traffic flows in a largescale network. We adopt the QoS-based Resource Allocation Model...