114 search results - page 5 / 23 » Hardware Acceleration of HMMER on FPGAs |
CHES
2009
Springer
14 years 8 months ago
2009
Springer
Abstract. This paper is devoted to the design of fast parallel accelerators for the cryptographic Tate pairing in characteristic three over supersingular elliptic curves. We propos...
ASAP
2009
IEEE
14 years 5 months ago
2009
IEEE
—This paper describes the acceleration of virtual ecology models using field-programmable gate arrays (FPGAs). Our approach targets models generated by the Virtual Ecology Workb...
SASP
2008
IEEE
14 years 2 months ago
2008
IEEE
—Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are F...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
By integrating one or more (hard or soft) CPU core on the chip, new generation platform FPGAs have become configurable systems on a chip (CSoC) that support a combined software an...
FPL
2007
Springer
14 years 2 months ago
2007
Springer
This paper describes an execution cache that uses process migration between hardware and software contexts by way of run-time reconfiguration (RTR) of Field Programmable Gate Arr...