112 search results - page 13 / 23 » Hardware Acceleration of Matrix Multiplication on a Xilinx F... |
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
The efficient design of multiplierless implementa- The goal is to find the optimal sub-expressions across all N dot tions of constant matrix multipliers is challenged by the huge p...
TVLSI
2010
13 years 2 months ago
2010
The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP...
SIGARCH
2010
13 years 2 months ago
2010
We describe a programming framework for high performance clusters with various hardware accelerators. In this framework, users can utilize the available heterogeneous resources pr...
CHES
2008
Springer
13 years 9 months ago
2008
Springer
Elliptic Curve Cryptosystems (ECC) have gained increasing acceptance in practice due to their significantly smaller bit size of the operands compared to other public-key cryptosyst...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...