Improving FPGA Performance for Carry-Save Arithmetic

The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP applications, and further opportunities to exploit it can be exposed through systematic data flow transformations that can be applied by a hardware compiler. Field-programmable gate arrays (FPGAs), however, are not particularly well suited to carry-save arithmetic. To address this concern, we introduce the "field programmable counter array" (FPCA), an accelerator for carry-save arithmetic intended for integration into an FPGA as an alternative to DSP blocks. In addition to multiplication and multiply accumulation, the FPCA can accelerate more general carry-save operations, such as multi-input addition (e.g., add 2 integers) and multipliers that have been fused with other adders. Our experiments show that the FPCA accelerates a wider variety of applications than DSP blocks and improves performance, ...

• Type: Journal
• Year: 2010
• Where: TVLSI
• Authors: Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Paolo Ienne
• Keywords: Artificial Intelligence, Carry-save Arithmetic, Field Programmable Counter, FPGA, TVLSI 2010