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PLDI
1999
ACM
15 years 6 months ago
Cache-Conscious Structure Layout
Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency hav...
Trishul M. Chilimbi, Mark D. Hill, James R. Larus
ISPASS
2006
IEEE
15 years 8 months ago
Friendly fire: understanding the effects of multiprocessor prefetches
Modern processors attempt to overcome increasing memory latencies by anticipating future references and prefetching those blocks from memory. The behavior and possible negative si...
Natalie D. Enright Jerger, Eric L. Hill, Mikko H. ...
IEEEPACT
2009
IEEE
15 years 9 months ago
Analytical Modeling of Pipeline Parallelism
Parallel programming is a requirement in the multi-core era. One of the most promising techniques to make parallel programming available for the general users is the use of parall...
Angeles G. Navarro, Rafael Asenjo, Siham Tabik, Ca...
ISCAS
2002
IEEE
154views Hardware» more  ISCAS 2002»
15 years 7 months ago
Architectural approaches to reduce leakage energy in caches
In this paper, we present two methods to reduce leakage energy by dynamically resizing the cache during program execution. The first method monitors the miss rate of the individua...
S. H. Tadas, C. Chakrabarti
112
Voted
ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
15 years 8 months ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock