230 search results - page 22 / 46 » Hardware Support for Control Transfers in Code Caches |
SIGARCH
2010
13 years 2 months ago
2010
We describe a programming framework for high performance clusters with various hardware accelerators. In this framework, users can utilize the available heterogeneous resources pr...
ASPLOS
2006
ACM
14 years 1 months ago
2006
ACM
Nested transactional memory (TM) facilitates software composition by letting one module invoke another without either knowing whether the other uses transactions. Closed nested tr...
FCCM
2005
IEEE
14 years 1 months ago
2005
IEEE
As technology sizes decrease and die area increases, designers are creating increasingly complex computing systems using FPGAs. To reduce design time for new products, the reuse o...
HIPEAC
2007
Springer
14 years 1 months ago
2007
Springer
A critical component in the design of secure processors is memory encryption which provides protection for the privacy of code and data stored in off-chip memory. The overhead of ...
ASPLOS
1998
ACM
13 years 11 months ago
1998
ACM
Optimizations aimed at reducing the impact of memory operations on execution speed have long concentrated on improving cache performance. These efforts achieve a reasonable level...