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» Hardware Support for Control Transfers in Code Caches
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LCTRTS
2004
Springer
14 years 29 days ago
Spinach: a liberty-based simulator for programmable network interface architectures
This paper presents Spinach, a new simulator toolset specifically designed to target programmable network interface architectures. Spinach models both system components that are ...
Paul Willmann, Michael Brogioli, Vijay S. Pai
LCTRTS
2009
Springer
14 years 2 months ago
Synergistic execution of stream programs on multicores with accelerators
The StreamIt programming model has been proposed to exploit parallelism in streaming applications on general purpose multicore architectures. The StreamIt graphs describe task, da...
Abhishek Udupa, R. Govindarajan, Matthew J. Thazhu...
EMSOFT
2006
Springer
13 years 11 months ago
Reliability mechanisms for file systems using non-volatile memory as a metadata store
Portable systems such as cell phones and portable media players commonly use non-volatile RAM (NVRAM) to hold all of their data and metadata, and larger systems can store metadata...
Kevin M. Greenan, Ethan L. Miller
CODES
2007
IEEE
14 years 1 months ago
A low power VLIW processor generation method by means of extracting non-redundant activation conditions
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuc...
ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
14 years 16 days ago
Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis
We introduce a new approach, “Dynamic Common Sub-expression Elimination (CSE)”, that dynamically eliminates common sub- expressions based on new opportunities created during s...
Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Ni...