In this paper we present a novel adder/subtracter arithmetic unit that combines Binary and Binary Code Decimal (BCD) operations. The proposed unit uses effective addition/subtract...
Humberto Calderon, Georgi Gaydadjiev, Stamatis Vas...
Reed-Solomon codes are an important class of error correcting codes used in many applications related to communications and digital storage. The fundamental operations in Reed-Sol...
Suman Mamidi, Daniel Iancu, Andrei Iancu, Michael ...
This paper? provides a description of our Network Time Interface M-Module NTI supporting high-accuracy external clock synchronization by hardware. The NTI is built around our custo...
The Imagine Stream Processor is a single-chip programmable media processor with 48 parallel ALUs. At 400 MHz, this translates to a peak arithmetic rate of 16 GFLOPS on single-prec...
Ujval J. Kapasi, William J. Dally, Scott Rixner, J...
This paper presents a method, called multiple constant multiplier trees MCMTs, for producing optimized recon gurable hardware implementations of vector products. An algorithm for ...