86 search results - page 10 / 18 » Hardware Support for Interval Arithmetic |
ASAP
2007
IEEE
15 years 7 months ago
2007
IEEE
In this paper we present a novel adder/subtracter arithmetic unit that combines Binary and Binary Code Decimal (BCD) operations. The proposed unit uses effective addition/subtract...
127
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ASAP
2005
IEEE
15 years 4 months ago
2005
IEEE
Reed-Solomon codes are an important class of error correcting codes used in many applications related to communications and digital storage. The fundamental operations in Reed-Sol...
106
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IPPS
1998
IEEE
15 years 7 months ago
1998
IEEE
This paper? provides a description of our Network Time Interface M-Module NTI supporting high-accuracy external clock synchronization by hardware. The NTI is built around our custo...
101
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ICCD
2002
IEEE
15 years 12 months ago
2002
IEEE
The Imagine Stream Processor is a single-chip programmable media processor with 48 parallel ALUs. At 400 MHz, this translates to a peak arithmetic rate of 16 GFLOPS on single-prec...
FCCM
1999
IEEE
15 years 7 months ago
1999
IEEE
This paper presents a method, called multiple constant multiplier trees MCMTs, for producing optimized recon gurable hardware implementations of vector products. An algorithm for ...