3902 search results - page 20 / 781 » Hardware Synthesis from C C Models |
DATE
2002
IEEE
14 years 21 days ago
2002
IEEE
In this paper, we present an efficient methodology to validate high performance algorithms and prototype them using reconfigurable hardware. We follow a strict topdown Hardware/So...
ICCD
2005
IEEE
14 years 1 months ago
2005
IEEE
— With the success of formal verification techniques like equivalence checking and model checking for hardware designs, there has been growing interest in applying such techniqu...
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In par...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
Rapid evaluation and design space exploration at the algorithmic level are important issues in the design cycle. In this paper we propose an original area vs delay estimation meth...