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» Hardware Synthesis from C C Models
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FPL
2004
Springer
101views Hardware» more  FPL 2004»
15 years 9 months ago
Automatic Creation of Reconfigurable PALs/PLAs for SoC
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run -time reconfigurabil...
Mark Holland, Scott Hauck
ISCAS
2007
IEEE
142views Hardware» more  ISCAS 2007»
15 years 10 months ago
Visualization of SystemC Designs
Complex designs can only be understood, if the underlying information is provided in a concise way. In this context visualization is becoming an essential part of system design, u...
Christian Genz, Rolf Drechsler, Gerhard Angst, Lot...
129
Voted
IPPS
1998
IEEE
15 years 7 months ago
Synthesis of a Systolic Array Genetic Algorithm
The paper presents the design of a hardware genetic algorithm which uses a pipeline of systolic arrays. Demostrated is the design methodology, where a simple genetic algorithm exp...
Graham M. Megson, I. M. Bland
147
Voted
ASAP
2005
IEEE
121views Hardware» more  ASAP 2005»
15 years 9 months ago
Using TLM for Exploring Bus-based SoC Communication Architectures
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
Sudeep Pasricha, Mohamed Ben-Romdhane
112
Voted
ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
15 years 9 months ago
Energy and latency evaluation of NoC topologies
Abstract — Mapping applications onto different networks-onchip (NoCs) topologies is done by mapping processing cores on local ports of routers considering requirements like laten...
Márcio Eduardo Kreutz, César A. M. M...