3902 search results - page 94 / 781 » Hardware Synthesis from C C Models |
JSA
2007
13 years 10 months ago
2007
This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high level hardware design and efficient hardware impleme...
DATE
2007
IEEE
14 years 4 months ago
2007
IEEE
Conventional high-level synthesis algorithms usually employ multi-cycle operators to reduce the cycle length in order to improve the circuit performance. These operators need seve...
PLDI
2012
ACM
12 years 20 days ago
2012
ACM
Modern architectures implement relaxed memory models which may reorder memory operations or execute them non-atomically. Special instructions called memory fences are provided, al...
ICRA
1999
IEEE
14 years 2 months ago
1999
IEEE
The modeling and control flexible-manufacturing workcells (FMCs) has generally been performed in a hierarchical structure, where at the highest level they have been modeled as dis...
ICCD
2006
IEEE
14 years 7 months ago
2006
IEEE
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...