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» Hardware Synthesis from Term Rewriting Systems
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FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
14 years 2 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 1 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
14 years 1 months ago
Tarantula: A Vector Extension to the Alpha Architecture
Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processo...
Roger Espasa, Federico Ardanaz, Julio Gago, Roger ...
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
14 years 23 days ago
Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches
In recent years, several alternative devices have been proposed to deal with inherent limitation of conventional CMOS devices in terms of scalability at nanometer scale geometry. ...
Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab
ISPD
2011
ACM
253views Hardware» more  ISPD 2011»
12 years 11 months ago
Assembling 2D blocks into 3D chips
Three-dimensional ICs promise to significantly extend the scale of system integration and facilitate new-generation electronics. However, progress in commercial 3D ICs has been s...
Johann Knechtel, Igor L. Markov, Jens Lienig