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ATS
2000
IEEE
98views Hardware» more  ATS 2000»
14 years 2 months ago
Embedded core testing using genetic algorithms
Testing of embedded cores is very difficult in SOC (system-on-a-chip), since the core user may not know the gate level implementation of the core, and the controllability and obse...
Ruofan Xu, Michael S. Hsiao
DATE
2000
IEEE
136views Hardware» more  DATE 2000»
14 years 2 months ago
On Applying Incremental Satisfiability to Delay Fault Testing
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah...
DATE
2000
IEEE
124views Hardware» more  DATE 2000»
14 years 2 months ago
On the Generation of Multiplexer Circuits for Pass Transistor Logic
Pass Transistor Logic has attracted more and more interest during last years, since it has proved to be an attractive alternative to static CMOS designs with respect to area, perf...
Christoph Scholl, Bernd Becker
ITC
2000
IEEE
101views Hardware» more  ITC 2000»
14 years 2 months ago
Reducing test data volume using external/LBIST hybrid test patterns
A common approachfor large industrial designs is to use logic built-in self-test (LBIST)followed by test data from an external tester. Because the fault coverage with LBIST alone ...
Debaleena Das, Nur A. Touba
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
14 years 2 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...