951 search results - page 43 / 191 » Hardware design experiences in ZebraNet |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
— This paper introduces a graph grammar based approach to automated topology synthesis of analog circuits. A grammar is developed to generate circuits through production rules, t...
ISQED
2003
IEEE
14 years 28 days ago
2003
IEEE
- This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a cha...
FPL
2000
Springer
13 years 11 months ago
2000
Springer
This paper discusses the design and implementation of finite state machines (FSM) with combinational circuits that are built primarily from RAM blocks. It suggests a novel state as...
ASAP
2008
IEEE
13 years 9 months ago
2008
IEEE
Automatic generation of custom instruction processors from high-level application descriptions enables fast design space exploration, while offering very favorable performance and...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper we present an approach to the design optimization of faulttolerant embedded systems for safety-critical applications. Processes are statically scheduled and communic...