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» Hardware design experiences in ZebraNet
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MSE
2005
IEEE
148views Hardware» more  MSE 2005»
14 years 1 months ago
Teaching System-Level Design Using SpecC and SystemC
System-level design of embedded computer systems is essential to manage complexity and enhance designer productivity. Viewing designs at t abstraction levels allows developers to ...
Robert D. Walstrom, Joseph Schneider, Diane T. Rov...
ISMVL
2010
IEEE
209views Hardware» more  ISMVL 2010»
14 years 23 days ago
Secure Design Flow for Asynchronous Multi-valued Logic Circuits
—The purpose of secure devices such as smartcards is to protect secret information against software and hardware attacks. Implementation of the appropriate protection techniques ...
Ashur Rafiev, Julian P. Murphy, Alexandre Yakovlev
ICCAD
2004
IEEE
113views Hardware» more  ICCAD 2004»
14 years 4 months ago
Static statistical timing analysis for latch-based pipeline designs
A latch-based timing analyzer is an essential tool for developing high-speed pipeline designs. As process variations increasingly influence the timing characteristics of DSM desi...
Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, San...
DATE
2007
IEEE
123views Hardware» more  DATE 2007»
14 years 2 months ago
Clock domain crossing fault model and coverage metric for validation of SoC design
Multiple asynchronous clock domains have been increasingly employed in System-on-Chip (SoC) designs for different I/O interfaces. Functional validation is one of the most expensiv...
Yi Feng 0002, Zheng Zhou, Dong Tong, Xu Cheng
ICCD
2006
IEEE
107views Hardware» more  ICCD 2006»
14 years 4 months ago
Design and Implementation of the TRIPS Primary Memory System
Abstract— In this paper, we describe the design and implementation of the primary memory system of the TRIPS processor. To match the aggressive execution bandwidth and support hi...
Simha Sethumadhavan, Robert G. McDonald, Rajagopal...