951 search results - page 78 / 191 » Hardware design experiences in ZebraNet |
ASPDAC
2009
ACM
14 years 4 months ago
2009
ACM
- With increasing availability of predefined IP (Intellectual Properties) blocks and inexpensive microprocessors, embedded system designers are faced with more design choices than ...
DATE
2007
IEEE
14 years 4 months ago
2007
IEEE
1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...
SBACPAD
2007
IEEE
14 years 4 months ago
2007
IEEE
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
DATE
2002
IEEE
14 years 3 months ago
2002
IEEE
An incremental simulation-based approach to fault diagnosis and logic debugging is presented. During each iteration of the algorithm, a single suspicious location is identified a...
ISSS
2002
IEEE
14 years 3 months ago
2002
IEEE
Message-passing mechanism is commonly used to preserve data coherency in distributed systems. This paper presents an algorithm for insertion of minimal message-passing in system-l...